diff --git a/PCB_SMD/README.md b/PCB_SMD/README.md
index a426688..11f5c2b 100644
--- a/PCB_SMD/README.md
+++ b/PCB_SMD/README.md
@@ -10,4 +10,4 @@ PCB for the TinyLora Sensor Node, SMD Version
 *  2x SMD 1206 Ceramic Capacitor (~100nF), optional
 *  SMD 1206 LED and fitting SMD 1206 Current Limiting Resistor, optional
 *  2x3 Pin 2.54mm Pitch Pinheader for PRG1 (has to be shortened to fit into the case), optional
-*  1x8 Pin 2.54mm Pitch Pinheader for J1 (optional, only if not meant to be put into the case)
\ No newline at end of file
+*  1x8 Pin 2.54mm Pitch Pinheader for J1 (only if not meant to be put into the case), optional
diff --git a/PCB_THT/Gerber/LORA_ATTINY84-B_Cu.gbr b/PCB_THT/Gerber/LORA_ATTINY84-B_Cu.gbr
new file mode 100644
index 0000000..f15d46f
--- /dev/null
+++ b/PCB_THT/Gerber/LORA_ATTINY84-B_Cu.gbr
@@ -0,0 +1,1535 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.4*
+G04 #@! TF.CreationDate,2019-09-02T21:27:03+02:00*
+G04 #@! TF.ProjectId,LORA_ATTINY84,4c4f5241-5f41-4545-9449-4e5938342e6b,rev?*
+G04 #@! TF.SameCoordinates,Original*
+G04 #@! TF.FileFunction,Copper,L2,Bot*
+G04 #@! TF.FilePolarity,Positive*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 5.1.4) date 2019-09-02 21:27:03*
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+G04 APERTURE END LIST*
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diff --git a/PCB_THT/Gerber/LORA_ATTINY84-B_Mask.gbr b/PCB_THT/Gerber/LORA_ATTINY84-B_Mask.gbr
new file mode 100644
index 0000000..69f46ba
--- /dev/null
+++ b/PCB_THT/Gerber/LORA_ATTINY84-B_Mask.gbr
@@ -0,0 +1,1011 @@
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+G04 #@! TF.FileFunction,Soldermask,Bot*
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diff --git a/PCB_THT/Gerber/LORA_ATTINY84-B_Paste.gbr b/PCB_THT/Gerber/LORA_ATTINY84-B_Paste.gbr
new file mode 100644
index 0000000..b35ac0e
--- /dev/null
+++ b/PCB_THT/Gerber/LORA_ATTINY84-B_Paste.gbr
@@ -0,0 +1,14 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.4*
+G04 #@! TF.CreationDate,2019-09-02T21:27:03+02:00*
+G04 #@! TF.ProjectId,LORA_ATTINY84,4c4f5241-5f41-4545-9449-4e5938342e6b,rev?*
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+G04 #@! TF.FileFunction,Paste,Bot*
+G04 #@! TF.FilePolarity,Positive*
+%FSLAX46Y46*%
+G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
+G04 Created by KiCad (PCBNEW 5.1.4) date 2019-09-02 21:27:03*
+%MOMM*%
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diff --git a/PCB_THT/Gerber/LORA_ATTINY84-B_SilkS.gbr b/PCB_THT/Gerber/LORA_ATTINY84-B_SilkS.gbr
new file mode 100644
index 0000000..6933af7
--- /dev/null
+++ b/PCB_THT/Gerber/LORA_ATTINY84-B_SilkS.gbr
@@ -0,0 +1,14 @@
+G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.1.4*
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diff --git a/PCB_THT/Gerber/LORA_ATTINY84-Edge_Cuts.gbr b/PCB_THT/Gerber/LORA_ATTINY84-Edge_Cuts.gbr
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index 0000000..5274976
--- /dev/null
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diff --git a/PCB_THT/Gerber/LORA_ATTINY84-NPTH.drl b/PCB_THT/Gerber/LORA_ATTINY84-NPTH.drl
new file mode 100644
index 0000000..bb4fbac
--- /dev/null
+++ b/PCB_THT/Gerber/LORA_ATTINY84-NPTH.drl
@@ -0,0 +1,13 @@
+M48
+; DRILL file {KiCad 5.1.4} date Mo 02 Sep 2019 21:27:11 CEST
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2019-09-02T21:27:11+02:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.4
+; #@! TF.FileFunction,NonPlated,1,2,NPTH
+FMAT,2
+INCH
+%
+G90
+G05
+T0
+M30
diff --git a/PCB_THT/Gerber/LORA_ATTINY84-PTH.drl b/PCB_THT/Gerber/LORA_ATTINY84-PTH.drl
new file mode 100644
index 0000000..40441e2
--- /dev/null
+++ b/PCB_THT/Gerber/LORA_ATTINY84-PTH.drl
@@ -0,0 +1,51 @@
+M48
+; DRILL file {KiCad 5.1.4} date Mo 02 Sep 2019 21:27:11 CEST
+; FORMAT={-:-/ absolute / inch / decimal}
+; #@! TF.CreationDate,2019-09-02T21:27:11+02:00
+; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.4
+; #@! TF.FileFunction,Plated,1,2,PTH
+FMAT,2
+INCH
+T1C0.0157
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+%
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diff --git a/PCB_THT/LORA_ATTINY84-cache.lib b/PCB_THT/LORA_ATTINY84-cache.lib
new file mode 100644
index 0000000..d38d2d0
--- /dev/null
+++ b/PCB_THT/LORA_ATTINY84-cache.lib
@@ -0,0 +1,166 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Connector_Conn_01x08_Male
+#
+DEF Connector_Conn_01x08_Male J 0 40 Y N 1 F N
+F0 "J" 0 400 50 H V C CNN
+F1 "Connector_Conn_01x08_Male" 0 -500 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S 34 -395 0 -405 1 1 6 F
+S 34 -295 0 -305 1 1 6 F
+S 34 -195 0 -205 1 1 6 F
+S 34 -95 0 -105 1 1 6 F
+S 34 5 0 -5 1 1 6 F
+S 34 105 0 95 1 1 6 F
+S 34 205 0 195 1 1 6 F
+S 34 305 0 295 1 1 6 F
+P 2 1 1 6 50 -400 34 -400 N
+P 2 1 1 6 50 -300 34 -300 N
+P 2 1 1 6 50 -200 34 -200 N
+P 2 1 1 6 50 -100 34 -100 N
+P 2 1 1 6 50 0 34 0 N
+P 2 1 1 6 50 100 34 100 N
+P 2 1 1 6 50 200 34 200 N
+P 2 1 1 6 50 300 34 300 N
+X Pin_1 1 200 300 150 L 50 50 1 1 P
+X Pin_2 2 200 200 150 L 50 50 1 1 P
+X Pin_3 3 200 100 150 L 50 50 1 1 P
+X Pin_4 4 200 0 150 L 50 50 1 1 P
+X Pin_5 5 200 -100 150 L 50 50 1 1 P
+X Pin_6 6 200 -200 150 L 50 50 1 1 P
+X Pin_7 7 200 -300 150 L 50 50 1 1 P
+X Pin_8 8 200 -400 150 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_Antenna
+#
+DEF Device_Antenna AE 0 40 N N 1 F N
+F0 "AE" -75 75 50 H V R CNN
+F1 "Device_Antenna" -75 0 50 H V R CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 1 10 0 100 0 -150 N
+P 3 0 1 10 50 100 0 -100 -50 100 N
+X A 1 0 -200 100 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Device_Battery_Cell
+#
+DEF Device_Battery_Cell BT 0 0 N N 1 F N
+F0 "BT" 100 100 50 H V L CNN
+F1 "Device_Battery_Cell" 100 0 50 H V L CNN
+F2 "" 0 60 50 V I C CNN
+F3 "" 0 60 50 V I C CNN
+DRAW
+S -90 70 90 60 0 1 0 F
+S -62 47 58 27 0 1 0 F
+P 2 0 1 0 0 30 0 0 N
+P 2 0 1 0 0 70 0 100 N
+P 2 0 1 10 20 135 60 135 N
+P 2 0 1 10 40 155 40 115 N
+X + 1 0 200 100 D 50 50 1 1 P
+X - 2 0 -100 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# MCU_Microchip_ATtiny_ATtiny84A-SSU
+#
+DEF MCU_Microchip_ATtiny_ATtiny84A-SSU U 0 20 Y Y 1 F N
+F0 "U" -500 850 50 H V L BNN
+F1 "MCU_Microchip_ATtiny_ATtiny84A-SSU" 100 -850 50 H V L TNN
+F2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" 0 0 50 H I C CIN
+F3 "" 0 0 50 H I C CNN
+ALIAS ATtiny24-20SSU ATtiny24A-SSU ATtiny44V-10SSU ATtiny44-20SSU ATtiny44A-SSU ATtiny84V-10SSU ATtiny84-20SSU ATtiny84A-SSU
+$FPLIST
+ SOIC*3.9x8.7mm*P1.27mm*
+$ENDFPLIST
+DRAW
+S -500 -800 500 800 0 1 10 f
+X VCC 1 0 900 100 D 50 50 1 1 W
+X PA3 10 600 300 100 L 50 50 1 1 T
+X PA2 11 600 400 100 L 50 50 1 1 T
+X PA1 12 600 500 100 L 50 50 1 1 T
+X AREF/PA0 13 600 600 100 L 50 50 1 1 T
+X GND 14 0 -900 100 U 50 50 1 1 W
+X XTAL1/PB0 2 600 -300 100 L 50 50 1 1 T
+X XTAL2/PB1 3 600 -400 100 L 50 50 1 1 T
+X ~RESET~/PB3 4 600 -600 100 L 50 50 1 1 T
+X PB2 5 600 -500 100 L 50 50 1 1 T
+X PA7 6 600 -100 100 L 50 50 1 1 T
+X PA6 7 600 0 100 L 50 50 1 1 T
+X PA5 8 600 100 100 L 50 50 1 1 T
+X PA4 9 600 200 100 L 50 50 1 1 T
+ENDDRAW
+ENDDEF
+#
+# RF_Module_RFM95W-868S2
+#
+DEF RF_Module_RFM95W-868S2 U 0 40 Y Y 1 F N
+F0 "U" -410 460 50 H V L CNN
+F1 "RF_Module_RFM95W-868S2" 60 450 50 H V L CNN
+F2 "" -3300 1650 50 H I C CNN
+F3 "" -3300 1650 50 H I C CNN
+ALIAS RFM95W-915S2 RFM96W-315S2 RFM96W-433S2 RFM97W-868S2 RFM97W-915S2 RFM98W-315S2 RFM98W-433S2 RFM69HCW
+$FPLIST
+ HOPERF*RFM9XW*
+$ENDFPLIST
+DRAW
+S -400 400 400 -500 0 1 10 f
+X GND 1 -100 -600 100 U 50 50 1 1 W
+X GND 10 100 -600 100 U 50 50 1 1 W
+X DIO3 11 500 -100 100 L 50 50 1 1 B
+X DIO4 12 500 0 100 L 50 50 1 1 B
+X 3.3V 13 0 500 100 D 50 50 1 1 W
+X DIO0 14 500 -400 100 L 50 50 1 1 B
+X DIO1 15 500 -300 100 L 50 50 1 1 B
+X DIO2 16 500 -200 100 L 50 50 1 1 B
+X MISO 2 -500 100 100 R 50 50 1 1 O
+X MOSI 3 -500 200 100 R 50 50 1 1 I
+X SCK 4 -500 300 100 R 50 50 1 1 I
+X NSS 5 -500 0 100 R 50 50 1 1 I
+X RESET 6 -500 -200 100 R 50 50 1 1 B
+X DIO5 7 500 100 100 L 50 50 1 1 B
+X GND 8 0 -600 100 U 50 50 1 1 W
+X ANT 9 500 300 100 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# power_+3V3
+#
+DEF power_+3V3 #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "power_+3V3" 0 140 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS +3.3V
+DRAW
+P 2 0 1 0 -30 50 0 100 N
+P 2 0 1 0 0 0 0 100 N
+P 2 0 1 0 0 100 30 50 N
+X +3V3 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# power_GND
+#
+DEF power_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/PCB_THT/LORA_ATTINY84.kicad_pcb b/PCB_THT/LORA_ATTINY84.kicad_pcb
new file mode 100644
index 0000000..cc27f8f
--- /dev/null
+++ b/PCB_THT/LORA_ATTINY84.kicad_pcb
@@ -0,0 +1,878 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.1.4)
+
+  (general
+    (thickness 1.6)
+    (drawings 5)
+    (tracks 72)
+    (zones 0)
+    (modules 5)
+    (nets 15)
+  )
+
+  (page A4)
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (32 B.Adhes user)
+    (33 F.Adhes user)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (41 Cmts.User user)
+    (42 Eco1.User user)
+    (43 Eco2.User user)
+    (44 Edge.Cuts user)
+    (45 Margin user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.25)
+    (trace_clearance 0.2)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.2)
+    (via_size 0.8)
+    (via_drill 0.4)
+    (via_min_size 0.4)
+    (via_min_drill 0.3)
+    (uvia_size 0.3)
+    (uvia_drill 0.1)
+    (uvias_allowed no)
+    (uvia_min_size 0.2)
+    (uvia_min_drill 0.1)
+    (edge_width 0.05)
+    (segment_width 0.2)
+    (pcb_text_width 0.3)
+    (pcb_text_size 1.5 1.5)
+    (mod_edge_width 0.12)
+    (mod_text_size 1 1)
+    (mod_text_width 0.15)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.051)
+    (solder_mask_min_width 0.25)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFDFF7F)
+    (pcbplotparams
+      (layerselection 0x010fc_ffffffff)
+      (usegerberextensions false)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "Gerber/"))
+  )
+
+  (net 0 "")
+  (net 1 "Net-(AE1-Pad1)")
+  (net 2 GND)
+  (net 3 +3V3)
+  (net 4 PB2)
+  (net 5 PA7)
+  (net 6 PA3)
+  (net 7 PA2)
+  (net 8 PA1)
+  (net 9 PA0)
+  (net 10 MISO)
+  (net 11 SCK)
+  (net 12 MOSI)
+  (net 13 DIO0)
+  (net 14 NSS)
+
+  (net_class Default "Dies ist die voreingestellte Netzklasse."
+    (clearance 0.2)
+    (trace_width 0.25)
+    (via_dia 0.8)
+    (via_drill 0.4)
+    (uvia_dia 0.3)
+    (uvia_drill 0.1)
+    (add_net +3V3)
+    (add_net DIO0)
+    (add_net GND)
+    (add_net MISO)
+    (add_net MOSI)
+    (add_net NSS)
+    (add_net "Net-(AE1-Pad1)")
+    (add_net PA0)
+    (add_net PA1)
+    (add_net PA2)
+    (add_net PA3)
+    (add_net PA7)
+    (add_net PB2)
+    (add_net SCK)
+  )
+
+  (module battery_holder:BatteryHolder_Keystone_1060_1x2032_Long_Pad (layer F.Cu) (tedit 5D66CD14) (tstamp 5D66BC43)
+    (at 56.515 60.96 90)
+    (descr http://www.keyelco.com/product-pdf.cfm?p=726)
+    (tags "CR2032 BR2032 BatteryHolder Battery")
+    (path /5D6F40EE)
+    (attr smd)
+    (fp_text reference BT1 (at -14.125 -5.3 90) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Battery_Cell (at 0 -11.75 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_circle (center 0 0) (end -10.2 0) (layer Dwgs.User) (width 0.3))
+    (fp_line (start 11 8) (end -9.4 8) (layer F.Fab) (width 0.1))
+    (fp_line (start 11 -8) (end -11 -8) (layer F.Fab) (width 0.1))
+    (fp_line (start 11 8) (end 11 3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start 11 -8) (end 11 -3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -11 -8) (end -11 -3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -11 6.4) (end -11 3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -11 3.5) (end -14.2 3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -14.2 3.5) (end -14.2 -3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -14.2 -3.5) (end -11 -3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start 11 3.5) (end 14.2 3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.2 3.5) (end 14.2 -3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start 14.2 -3.5) (end 11 -3.5) (layer F.Fab) (width 0.1))
+    (fp_line (start -9.4 8) (end -11 6.4) (layer F.Fab) (width 0.1))
+    (fp_line (start 11.35 3.85) (end 14.55 3.85) (layer F.SilkS) (width 0.12))
+    (fp_line (start 14.55 3.85) (end 14.55 2.3) (layer F.SilkS) (width 0.12))
+    (fp_line (start 11.35 8.35) (end 11.35 3.85) (layer F.SilkS) (width 0.12))
+    (fp_line (start 11.35 8.35) (end -9.55 8.35) (layer F.SilkS) (width 0.12))
+    (fp_line (start -11.35 6.55) (end -11.35 3.85) (layer F.SilkS) (width 0.12))
+    (fp_line (start -9.55 8.35) (end -11.35 6.55) (layer F.SilkS) (width 0.12))
+    (fp_line (start -11.35 3.85) (end -14.55 3.85) (layer F.SilkS) (width 0.12))
+    (fp_line (start -14.55 3.85) (end -14.55 2.3) (layer F.SilkS) (width 0.12))
+    (fp_line (start -11.35 -3.85) (end -14.55 -3.85) (layer F.SilkS) (width 0.12))
+    (fp_line (start -14.55 -3.85) (end -14.55 -2.3) (layer F.SilkS) (width 0.12))
+    (fp_line (start 11.35 -3.85) (end 14.55 -3.85) (layer F.SilkS) (width 0.12))
+    (fp_line (start 14.55 -3.85) (end 14.55 -2.3) (layer F.SilkS) (width 0.12))
+    (fp_line (start -11.35 -8.35) (end 11.35 -8.35) (layer F.SilkS) (width 0.12))
+    (fp_line (start -11.35 -8.35) (end -11.35 -3.85) (layer F.SilkS) (width 0.12))
+    (fp_line (start 11.35 -8.35) (end 11.35 -3.85) (layer F.SilkS) (width 0.12))
+    (fp_arc (start 0 0) (end -6.5 8.5) (angle -74.81070976) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 11.5 8.5) (end 6.5 8.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -6.5 8.5) (end -11.5 8.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -11.5 4) (end -11.5 8.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -14.7 4) (end -11.5 4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -14.7 4) (end -14.7 2.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -14.7 2.3) (end -16.45 2.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -16.45 2.3) (end -16.45 -2.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -14.7 -2.3) (end -16.45 -2.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -14.7 -2.3) (end -14.7 -4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -14.7 -4) (end -11.5 -4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -11.5 -4) (end -11.5 -8.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -11.5 -8.5) (end -6.5 -8.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 11.5 -8.5) (end 11.5 -4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 11.5 -4) (end 14.7 -4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 14.7 -4) (end 14.7 -2.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 14.7 -2.3) (end 16.45 -2.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 16.45 -2.3) (end 16.45 2.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 16.45 2.3) (end 14.7 2.3) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 14.7 2.3) (end 14.7 4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 14.7 4) (end 11.5 4) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 11.5 4) (end 11.5 8.5) (layer F.CrtYd) (width 0.05))
+    (fp_arc (start 0 0) (end 6.5 -8.5) (angle -74.81070976) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 11.5 -8.5) (end 6.5 -8.5) (layer F.CrtYd) (width 0.05))
+    (fp_text user BAT (at 0 0 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -13 5) (end -13 7) (layer F.SilkS) (width 0.12))
+    (fp_line (start -12 6) (end -14 6) (layer F.SilkS) (width 0.12))
+    (pad 2 smd rect (at 12.446 0 270) (size 7.1 3.6) (layers F.Cu F.Paste F.Mask)
+      (net 2 GND))
+    (pad 1 smd rect (at -12.446 0 270) (size 7.1 3.6) (layers F.Cu F.Paste F.Mask)
+      (net 3 +3V3))
+    (model ${KISYS3DMOD}/Battery.3dshapes/BatteryHolder_Keystone_1060_1x2032.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Connector_PinSocket_2.54mm:PinSocket_1x08_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A420) (tstamp 5D66B938)
+    (at 89.535 48.895)
+    (descr "Through hole straight socket strip, 1x08, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
+    (tags "Through hole socket strip THT 1x08 2.54mm single row")
+    (path /5D68DC89)
+    (fp_text reference J1 (at 0 -2.77) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Sensor (at 0 20.55) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -0.635) (end 1.27 19.05) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 19.05) (end -1.27 19.05) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 19.05) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 19.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 19.11) (end 1.33 19.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 19.11) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
+    (fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.75 -1.8) (end 1.75 19.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.75 19.55) (end -1.8 19.55) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 19.55) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_text user %R (at 0 8.89 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 4 PB2))
+    (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 5 PA7))
+    (pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 6 PA3))
+    (pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 7 PA2))
+    (pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 8 PA1))
+    (pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 9 PA0))
+    (pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 2 GND))
+    (pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 3 +3V3))
+    (model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x08_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module Package_DIP:DIP-14_W7.62mm_Socket (layer F.Cu) (tedit 5A02E8C5) (tstamp 5D6691B9)
+    (at 84.455 46.355 270)
+    (descr "14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket")
+    (tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket")
+    (path /5D66342E)
+    (fp_text reference U1 (at 3.81 7.62 180) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value ATtiny84A-SSU (at 3.81 17.57 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user ATTiny84 (at 3.81 7.62 180) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 9.15 16.85) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.55 16.85) (end 9.15 16.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.55 -1.6) (end -1.55 16.85) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 8.95 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12))
+    (fp_line (start 8.95 16.63) (end 8.95 -1.39) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 16.63) (end 8.95 16.63) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 -1.39) (end -1.33 16.63) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 6.46 16.57) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 16.57) (end 6.46 16.57) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.16 -1.33) (end 1.16 16.57) (layer F.SilkS) (width 0.12))
+    (fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1))
+    (fp_line (start 8.89 16.57) (end 8.89 -1.33) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 16.57) (end 8.89 16.57) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 -1.33) (end -1.27 16.57) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 0.635 16.51) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.985 16.51) (end 0.635 16.51) (layer F.Fab) (width 0.1))
+    (fp_line (start 6.985 -1.27) (end 6.985 16.51) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
+    (fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
+    (pad 14 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 2 GND))
+    (pad 7 thru_hole oval (at 0 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 12 MOSI))
+    (pad 13 thru_hole oval (at 7.62 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 9 PA0))
+    (pad 6 thru_hole oval (at 0 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 5 PA7))
+    (pad 12 thru_hole oval (at 7.62 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 8 PA1))
+    (pad 5 thru_hole oval (at 0 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 4 PB2))
+    (pad 11 thru_hole oval (at 7.62 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 7 PA2))
+    (pad 4 thru_hole oval (at 0 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
+    (pad 10 thru_hole oval (at 7.62 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 6 PA3))
+    (pad 3 thru_hole oval (at 0 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 14 NSS))
+    (pad 9 thru_hole oval (at 7.62 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 11 SCK))
+    (pad 2 thru_hole oval (at 0 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 13 DIO0))
+    (pad 8 thru_hole oval (at 7.62 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 10 MISO))
+    (pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
+      (net 3 +3V3))
+    (model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-14_W7.62mm_Socket.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (module RFM:RFM95 (layer F.Cu) (tedit 585E5D4C) (tstamp 5D66B997)
+    (at 68.58 59.309)
+    (path /5D664943)
+    (fp_text reference U2 (at 8.255 8.001) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value RFM95W-868S2 (at 7.62 7.62) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 0 -1) (end 16 -1) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 10.8) (end 0 11.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 8.8) (end 0 9.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 6.8) (end 0 7.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 4.8) (end 0 5.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 3.2) (end 0 2.8) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 1.2) (end 0 0.8) (layer F.SilkS) (width 0.2))
+    (fp_line (start -1 -0.8) (end 0 -0.8) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 -0.8) (end 0 -1) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 12.8) (end 0 13.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 -1) (end 16 -0.8) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 0.8) (end 16 1.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 2.8) (end 16 3.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 4.8) (end 16 5.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 6.8) (end 16 7.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 8.8) (end 16 9.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 10.8) (end 16 11.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 12.8) (end 16 13.2) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 14.8) (end 16 15) (layer F.SilkS) (width 0.2))
+    (fp_line (start 16 15) (end 0 15) (layer F.SilkS) (width 0.2))
+    (fp_line (start 0 15) (end 0 14.8) (layer F.SilkS) (width 0.2))
+    (pad 16 smd oval (at 16 0) (size 2 1) (layers F.Cu F.Paste F.Mask))
+    (pad 15 smd oval (at 16 2) (size 2 1) (layers F.Cu F.Paste F.Mask))
+    (pad 14 smd oval (at 16 4) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 13 DIO0))
+    (pad 13 smd oval (at 16 6) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 3 +3V3))
+    (pad 12 smd oval (at 16 8) (size 2 1) (layers F.Cu F.Paste F.Mask))
+    (pad 11 smd oval (at 16 10) (size 2 1) (layers F.Cu F.Paste F.Mask))
+    (pad 10 smd oval (at 16 12) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 2 GND))
+    (pad 9 smd oval (at 16 14) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 1 "Net-(AE1-Pad1)"))
+    (pad 8 smd oval (at 0 14) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 2 GND))
+    (pad 7 smd oval (at 0 12) (size 2 1) (layers F.Cu F.Paste F.Mask))
+    (pad 6 smd oval (at 0 10) (size 2 1) (layers F.Cu F.Paste F.Mask))
+    (pad 5 smd oval (at 0 8) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 14 NSS))
+    (pad 4 smd oval (at 0 6) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 11 SCK))
+    (pad 3 smd oval (at 0 4) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 10 MISO))
+    (pad 2 smd oval (at 0 2) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 12 MOSI))
+    (pad 1 smd oval (at 0 0) (size 2 1) (layers F.Cu F.Paste F.Mask)
+      (net 2 GND))
+  )
+
+  (module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5D66B8BC)
+    (at 89.535 73.279 180)
+    (descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
+    (tags "Through hole pin header THT 1x01 2.54mm single row")
+    (path /5D699DFD)
+    (fp_text reference AE1 (at 0 -2.33) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value Antenna (at 0 2.33) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text user %R (at 0 0 90) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
+    (fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
+    (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
+    (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
+    (pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
+      (net 1 "Net-(AE1-Pad1)"))
+    (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
+      (at (xyz 0 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
+  (gr_text "TinyLora-DIL V1" (at 76.835 76.2) (layer F.SilkS)
+    (effects (font (size 1 1) (thickness 0.15)))
+  )
+  (gr_line (start 92.075 43.18) (end 45.72 43.18) (layer Edge.Cuts) (width 0.05) (tstamp 5D66E377))
+  (gr_line (start 92.075 78.74) (end 92.075 43.18) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 45.72 78.74) (end 92.075 78.74) (layer Edge.Cuts) (width 0.05))
+  (gr_line (start 45.72 43.18) (end 45.72 78.74) (layer Edge.Cuts) (width 0.05))
+
+  (segment (start 89.505 73.309) (end 89.535 73.279) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 84.58 73.309) (end 89.505 73.309) (width 0.25) (layer F.Cu) (net 1))
+  (segment (start 68.58 59.309) (end 69.469 59.309) (width 0.25) (layer F.Cu) (net 2))
+  (via (at 69.85 59.69) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 2))
+  (segment (start 69.469 59.309) (end 69.85 59.69) (width 0.25) (layer F.Cu) (net 2))
+  (via (at 69.85 73.66) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 2))
+  (segment (start 68.58 73.309) (end 69.499 73.309) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 69.499 73.309) (end 69.85 73.66) (width 0.25) (layer F.Cu) (net 2))
+  (via (at 83.185 71.755) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 2))
+  (segment (start 84.58 71.309) (end 83.631 71.309) (width 0.25) (layer F.Cu) (net 2))
+  (segment (start 83.631 71.309) (end 83.185 71.755) (width 0.25) (layer F.Cu) (net 2))
+  (via (at 56.515 52.705) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 2))
+  (segment (start 56.515 48.514) (end 56.515 52.705) (width 0.25) (layer F.Cu) (net 2))
+  (via (at 74.295 48.895) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 4))
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diff --git a/PCB_THT/LORA_ATTINY84.net b/PCB_THT/LORA_ATTINY84.net
new file mode 100644
index 0000000..b4ea7e9
--- /dev/null
+++ b/PCB_THT/LORA_ATTINY84.net
@@ -0,0 +1,285 @@
+(export (version D)
+  (design
+    (source /data/Git/IOT/LORA_ATTINY84/LORA_ATTINY84.sch)
+    (date "Mi 28 Aug 2019 10:33:34 CEST")
+    (tool "Eeschema 5.1.4")
+    (sheet (number 1) (name /) (tstamps /)
+      (title_block
+        (title)
+        (company)
+        (rev)
+        (date)
+        (source LORA_ATTINY84.sch)
+        (comment (number 1) (value ""))
+        (comment (number 2) (value ""))
+        (comment (number 3) (value ""))
+        (comment (number 4) (value "")))))
+  (components
+    (comp (ref U1)
+      (value ATtiny84A-SSU)
+      (footprint Package_SO:SOIC-14_3.9x8.7mm_P1.27mm)
+      (datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/doc8183.pdf)
+      (libsource (lib MCU_Microchip_ATtiny) (part ATtiny84A-SSU) (description "20MHz, 8kB Flash, 512B SRAM, 512B EEPROM, debugWIRE, SOIC-14"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5D66342E))
+    (comp (ref J1)
+      (value Sensor)
+      (footprint Connector_PinSocket_2.54mm:PinSocket_1x08_P2.54mm_Vertical)
+      (datasheet ~)
+      (libsource (lib Connector) (part Conn_01x08_Male) (description "Generic connector, single row, 01x08, script generated (kicad-library-utils/schlib/autogen/connector/)"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5D68DC89))
+    (comp (ref AE1)
+      (value Antenna)
+      (footprint Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Horizontal)
+      (datasheet ~)
+      (libsource (lib Device) (part Antenna) (description Antenna))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5D699DFD))
+    (comp (ref C2)
+      (value 100n)
+      (footprint Capacitor_SMD:C_1206_3216Metric_Pad1.42x1.75mm_HandSolder)
+      (datasheet ~)
+      (libsource (lib Device) (part C) (description "Unpolarized capacitor"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5D6B1612))
+    (comp (ref C1)
+      (value 100n)
+      (footprint Capacitor_SMD:C_1206_3216Metric_Pad1.42x1.75mm_HandSolder)
+      (datasheet ~)
+      (libsource (lib Device) (part C) (description "Unpolarized capacitor"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5D6B2940))
+    (comp (ref J2)
+      (value PRG)
+      (footprint Connector_PinSocket_2.54mm:PinSocket_2x03_P2.54mm_Vertical)
+      (datasheet ~)
+      (libsource (lib Connector_Generic) (part Conn_02x03_Odd_Even) (description "Generic connector, double row, 02x03, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5D69C5BF))
+    (comp (ref BT1)
+      (value Battery_Cell)
+      (footprint Battery:BatteryHolder_Keystone_1060_1x2032)
+      (datasheet ~)
+      (libsource (lib Device) (part Battery_Cell) (description "Single-cell battery"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5D6F40EE))
+    (comp (ref U2)
+      (value RFM95W-868S2)
+      (footprint RFM9X:RFM9X-TH)
+      (datasheet https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf)
+      (libsource (lib RF_Module) (part RFM95W-868S2) (description "Low power long range transceiver module, SPI and parallel interface, 868 MHz, spreading factor 6 to12, bandwith 7.8 to 500kHz, -111 to -148 dBm, SMD-16, DIP-16"))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 5D664943)))
+  (libparts
+    (libpart (lib Connector) (part Conn_01x08_Male)
+      (description "Generic connector, single row, 01x08, script generated (kicad-library-utils/schlib/autogen/connector/)")
+      (docs ~)
+      (footprints
+        (fp Connector*:*_1x??_*))
+      (fields
+        (field (name Reference) J)
+        (field (name Value) Conn_01x08_Male))
+      (pins
+        (pin (num 1) (name Pin_1) (type passive))
+        (pin (num 2) (name Pin_2) (type passive))
+        (pin (num 3) (name Pin_3) (type passive))
+        (pin (num 4) (name Pin_4) (type passive))
+        (pin (num 5) (name Pin_5) (type passive))
+        (pin (num 6) (name Pin_6) (type passive))
+        (pin (num 7) (name Pin_7) (type passive))
+        (pin (num 8) (name Pin_8) (type passive))))
+    (libpart (lib Connector_Generic) (part Conn_02x03_Odd_Even)
+      (description "Generic connector, double row, 02x03, odd/even pin numbering scheme (row 1 odd numbers, row 2 even numbers), script generated (kicad-library-utils/schlib/autogen/connector/)")
+      (docs ~)
+      (footprints
+        (fp Connector*:*_2x??_*))
+      (fields
+        (field (name Reference) J)
+        (field (name Value) Conn_02x03_Odd_Even))
+      (pins
+        (pin (num 1) (name Pin_1) (type passive))
+        (pin (num 2) (name Pin_2) (type passive))
+        (pin (num 3) (name Pin_3) (type passive))
+        (pin (num 4) (name Pin_4) (type passive))
+        (pin (num 5) (name Pin_5) (type passive))
+        (pin (num 6) (name Pin_6) (type passive))))
+    (libpart (lib Device) (part Antenna)
+      (description Antenna)
+      (docs ~)
+      (fields
+        (field (name Reference) AE)
+        (field (name Value) Antenna))
+      (pins
+        (pin (num 1) (name A) (type input))))
+    (libpart (lib Device) (part Battery_Cell)
+      (description "Single-cell battery")
+      (docs ~)
+      (fields
+        (field (name Reference) BT)
+        (field (name Value) Battery_Cell))
+      (pins
+        (pin (num 1) (name +) (type passive))
+        (pin (num 2) (name -) (type passive))))
+    (libpart (lib Device) (part C)
+      (description "Unpolarized capacitor")
+      (docs ~)
+      (footprints
+        (fp C_*))
+      (fields
+        (field (name Reference) C)
+        (field (name Value) C))
+      (pins
+        (pin (num 1) (name ~) (type passive))
+        (pin (num 2) (name ~) (type passive))))
+    (libpart (lib MCU_Microchip_ATtiny) (part ATtiny24V-10SSU)
+      (aliases
+        (alias ATtiny24-20SSU)
+        (alias ATtiny24A-SSU)
+        (alias ATtiny44V-10SSU)
+        (alias ATtiny44-20SSU)
+        (alias ATtiny44A-SSU)
+        (alias ATtiny84V-10SSU)
+        (alias ATtiny84-20SSU)
+        (alias ATtiny84A-SSU))
+      (description "10MHz, 2kB Flash, 128B SRAM, 128B EEPROM, debugWIRE, SOIC-14")
+      (docs http://ww1.microchip.com/downloads/en/DeviceDoc/doc8006.pdf)
+      (footprints
+        (fp SOIC*3.9x8.7mm*P1.27mm*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) ATtiny24V-10SSU)
+        (field (name Footprint) Package_SO:SOIC-14_3.9x8.7mm_P1.27mm))
+      (pins
+        (pin (num 1) (name VCC) (type power_in))
+        (pin (num 2) (name XTAL1/PB0) (type 3state))
+        (pin (num 3) (name XTAL2/PB1) (type 3state))
+        (pin (num 4) (name ~RESET~/PB3) (type 3state))
+        (pin (num 5) (name PB2) (type 3state))
+        (pin (num 6) (name PA7) (type 3state))
+        (pin (num 7) (name PA6) (type 3state))
+        (pin (num 8) (name PA5) (type 3state))
+        (pin (num 9) (name PA4) (type 3state))
+        (pin (num 10) (name PA3) (type 3state))
+        (pin (num 11) (name PA2) (type 3state))
+        (pin (num 12) (name PA1) (type 3state))
+        (pin (num 13) (name AREF/PA0) (type 3state))
+        (pin (num 14) (name GND) (type power_in))))
+    (libpart (lib RF_Module) (part RFM95W-868S2)
+      (aliases
+        (alias RFM95W-915S2)
+        (alias RFM96W-315S2)
+        (alias RFM96W-433S2)
+        (alias RFM97W-868S2)
+        (alias RFM97W-915S2)
+        (alias RFM98W-315S2)
+        (alias RFM98W-433S2)
+        (alias RFM69HCW))
+      (description "Low power long range transceiver module, SPI and parallel interface, 868 MHz, spreading factor 6 to12, bandwith 7.8 to 500kHz, -111 to -148 dBm, SMD-16, DIP-16")
+      (docs https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf)
+      (footprints
+        (fp HOPERF*RFM9XW*))
+      (fields
+        (field (name Reference) U)
+        (field (name Value) RFM95W-868S2))
+      (pins
+        (pin (num 1) (name GND) (type power_in))
+        (pin (num 2) (name MISO) (type output))
+        (pin (num 3) (name MOSI) (type input))
+        (pin (num 4) (name SCK) (type input))
+        (pin (num 5) (name NSS) (type input))
+        (pin (num 6) (name RESET) (type BiDi))
+        (pin (num 7) (name DIO5) (type BiDi))
+        (pin (num 8) (name GND) (type power_in))
+        (pin (num 9) (name ANT) (type BiDi))
+        (pin (num 10) (name GND) (type power_in))
+        (pin (num 11) (name DIO3) (type BiDi))
+        (pin (num 12) (name DIO4) (type BiDi))
+        (pin (num 13) (name 3.3V) (type power_in))
+        (pin (num 14) (name DIO0) (type BiDi))
+        (pin (num 15) (name DIO1) (type BiDi))
+        (pin (num 16) (name DIO2) (type BiDi)))))
+  (libraries
+    (library (logical Connector)
+      (uri /usr/share/kicad/library/Connector.lib))
+    (library (logical Connector_Generic)
+      (uri /usr/share/kicad/library/Connector_Generic.lib))
+    (library (logical Device)
+      (uri /usr/share/kicad/library/Device.lib))
+    (library (logical MCU_Microchip_ATtiny)
+      (uri /usr/share/kicad/library/MCU_Microchip_ATtiny.lib))
+    (library (logical RF_Module)
+      (uri /usr/share/kicad/library/RF_Module.lib)))
+  (nets
+    (net (code 1) (name +3V3)
+      (node (ref J1) (pin 8))
+      (node (ref BT1) (pin 1))
+      (node (ref U1) (pin 1))
+      (node (ref J2) (pin 2))
+      (node (ref C2) (pin 1))
+      (node (ref C1) (pin 2))
+      (node (ref U2) (pin 13)))
+    (net (code 2) (name GND)
+      (node (ref U2) (pin 1))
+      (node (ref U2) (pin 10))
+      (node (ref J1) (pin 7))
+      (node (ref BT1) (pin 2))
+      (node (ref C1) (pin 1))
+      (node (ref J2) (pin 6))
+      (node (ref C2) (pin 2))
+      (node (ref U1) (pin 14))
+      (node (ref U2) (pin 8)))
+    (net (code 3) (name "Net-(U2-Pad7)")
+      (node (ref U2) (pin 7)))
+    (net (code 4) (name DIO0)
+      (node (ref U1) (pin 2))
+      (node (ref U2) (pin 14)))
+    (net (code 5) (name "Net-(U2-Pad15)")
+      (node (ref U2) (pin 15)))
+    (net (code 6) (name "Net-(U2-Pad16)")
+      (node (ref U2) (pin 16)))
+    (net (code 7) (name NSS)
+      (node (ref U2) (pin 5))
+      (node (ref U1) (pin 3)))
+    (net (code 8) (name "Net-(U2-Pad6)")
+      (node (ref U2) (pin 6)))
+    (net (code 9) (name "Net-(AE1-Pad1)")
+      (node (ref AE1) (pin 1))
+      (node (ref U2) (pin 9)))
+    (net (code 10) (name "Net-(U2-Pad12)")
+      (node (ref U2) (pin 12)))
+    (net (code 11) (name "Net-(U2-Pad11)")
+      (node (ref U2) (pin 11)))
+    (net (code 12) (name PA3)
+      (node (ref U1) (pin 10))
+      (node (ref J1) (pin 3)))
+    (net (code 13) (name PA2)
+      (node (ref U1) (pin 11))
+      (node (ref J1) (pin 4)))
+    (net (code 14) (name PA1)
+      (node (ref U1) (pin 12))
+      (node (ref J1) (pin 5)))
+    (net (code 15) (name PA0)
+      (node (ref U1) (pin 13))
+      (node (ref J1) (pin 6)))
+    (net (code 16) (name PB2)
+      (node (ref J1) (pin 1))
+      (node (ref U1) (pin 5)))
+    (net (code 17) (name PA7)
+      (node (ref U1) (pin 6))
+      (node (ref J1) (pin 2)))
+    (net (code 19) (name MISO)
+      (node (ref J2) (pin 1))
+      (node (ref U1) (pin 8))
+      (node (ref U2) (pin 2)))
+    (net (code 20) (name SCK)
+      (node (ref J2) (pin 3))
+      (node (ref U1) (pin 9))
+      (node (ref U2) (pin 4)))
+    (net (code 21) (name MOSI)
+      (node (ref U1) (pin 7))
+      (node (ref J2) (pin 4))
+      (node (ref U2) (pin 3)))
+    (net (code 22) (name RST)
+      (node (ref J2) (pin 5))
+      (node (ref U1) (pin 4)))))
\ No newline at end of file
diff --git a/PCB_THT/LORA_ATTINY84.pro b/PCB_THT/LORA_ATTINY84.pro
new file mode 100644
index 0000000..e2d5b28
--- /dev/null
+++ b/PCB_THT/LORA_ATTINY84.pro
@@ -0,0 +1,248 @@
+update=Mi 28 Aug 2019 13:17:55 CEST
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=LORA_ATTINY84.net
+CopperLayerCount=2
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.2
+MinViaDiameter=0.4
+MinViaDrill=0.3
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.25
+ViaDiameter1=0.8
+ViaDrill1=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.12
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.05
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0.051
+SolderMaskMinWidth=0.25
+SolderPasteClearance=0
+SolderPasteRatio=0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=1
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=./
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
diff --git a/PCB_THT/LORA_ATTINY84.sch b/PCB_THT/LORA_ATTINY84.sch
new file mode 100644
index 0000000..d75b3e0
--- /dev/null
+++ b/PCB_THT/LORA_ATTINY84.sch
@@ -0,0 +1,248 @@
+EESchema Schematic File Version 4
+LIBS:LORA_ATTINY84-cache
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L power:GND #PWR0101
+U 1 1 5D662E21
+P 2550 4750
+F 0 "#PWR0101" H 2550 4500 50  0001 C CNN
+F 1 "GND" H 2555 4577 50  0000 C CNN
+F 2 "" H 2550 4750 50  0001 C CNN
+F 3 "" H 2550 4750 50  0001 C CNN
+	1    2550 4750
+	1    0    0    -1  
+$EndComp
+$Comp
+L MCU_Microchip_ATtiny:ATtiny84A-SSU U1
+U 1 1 5D66342E
+P 2550 3850
+F 0 "U1" H 2020 3896 50  0000 R CNN
+F 1 "ATtiny84A-SSU" H 2800 3850 50  0000 R CNN
+F 2 "Package_DIP:DIP-14_W7.62mm_Socket" H 2550 3850 50  0001 C CIN
+F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/doc8183.pdf" H 2550 3850 50  0001 C CNN
+	1    2550 3850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2900 1850 2900 1750
+$Comp
+L power:GND #PWR0103
+U 1 1 5D68B8DB
+P 3200 1750
+F 0 "#PWR0103" H 3200 1500 50  0001 C CNN
+F 1 "GND" H 3205 1577 50  0000 C CNN
+F 2 "" H 3200 1750 50  0001 C CNN
+F 3 "" H 3200 1750 50  0001 C CNN
+	1    3200 1750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3200 1650 3200 1750
+$Comp
+L Connector:Conn_01x08_Male J1
+U 1 1 5D68DC89
+P 4450 3500
+F 0 "J1" H 4422 3382 50  0000 R CNN
+F 1 "Sensor" V 4422 3473 50  0000 R CNN
+F 2 "Connector_PinSocket_2.54mm:PinSocket_1x08_P2.54mm_Vertical" H 4450 3500 50  0001 C CNN
+F 3 "~" H 4450 3500 50  0001 C CNN
+	1    4450 3500
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	2550 2900 2550 2950
+$Comp
+L Device:Antenna AE1
+U 1 1 5D699DFD
+P 2150 950
+F 0 "AE1" H 2230 939 50  0000 L CNN
+F 1 "Antenna" H 2230 848 50  0000 L CNN
+F 2 "Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical" H 2150 950 50  0001 C CNN
+F 3 "~" H 2150 950 50  0001 C CNN
+	1    2150 950 
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7350 7250 7350 7200
+Text GLabel 3150 3650 2    50   Input ~ 0
+SCK
+Text GLabel 3150 3750 2    50   Input ~ 0
+MISO
+Text GLabel 3150 3850 2    50   Input ~ 0
+MOSI
+Text GLabel 3150 4150 2    50   Input ~ 0
+DIO0
+Text GLabel 3150 4250 2    50   Input ~ 0
+NSS
+Text GLabel 3150 4450 2    50   Input ~ 0
+RST
+Text GLabel 2150 2150 3    50   Input ~ 0
+SCK
+Text GLabel 2350 2150 3    50   Input ~ 0
+MOSI
+Text GLabel 2250 2150 3    50   Input ~ 0
+MISO
+Text GLabel 2450 2150 3    50   Input ~ 0
+NSS
+Text GLabel 2850 1150 1    50   Input ~ 0
+DIO0
+Wire Wire Line
+	3050 1650 3100 1650
+Text GLabel 3150 3250 2    50   Input ~ 0
+PA0
+Text GLabel 3150 3350 2    50   Input ~ 0
+PA1
+Text GLabel 3150 3450 2    50   Input ~ 0
+PA2
+Text GLabel 3150 3550 2    50   Input ~ 0
+PA3
+Text GLabel 3150 3950 2    50   Input ~ 0
+PA7
+Text GLabel 3150 4350 2    50   Input ~ 0
+PB2
+Text GLabel 4250 3300 0    50   Input ~ 0
+PA0
+Text GLabel 4250 3400 0    50   Input ~ 0
+PA1
+Text GLabel 4250 3500 0    50   Input ~ 0
+PA2
+Text GLabel 4250 3600 0    50   Input ~ 0
+PA3
+Text GLabel 4250 3700 0    50   Input ~ 0
+PA7
+Text GLabel 4250 3800 0    50   Input ~ 0
+PB2
+$Comp
+L power:GND #PWR0102
+U 1 1 5D6F5F48
+P 3900 1600
+F 0 "#PWR0102" H 3900 1350 50  0001 C CNN
+F 1 "GND" H 3905 1427 50  0000 C CNN
+F 2 "" H 3900 1600 50  0001 C CNN
+F 3 "" H 3900 1600 50  0001 C CNN
+	1    3900 1600
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:Battery_Cell BT1
+U 1 1 5D6F40EE
+P 3900 1500
+F 0 "BT1" H 4018 1596 50  0000 L CNN
+F 1 "Battery_Cell" H 4018 1505 50  0000 L CNN
+F 2 "battery_holder:BatteryHolder_Keystone_1060_1x2032_Long_Pad" V 3900 1560 50  0001 C CNN
+F 3 "~" V 3900 1560 50  0001 C CNN
+	1    3900 1500
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+3V3 #PWR0105
+U 1 1 5D6F66AA
+P 3900 1300
+F 0 "#PWR0105" H 3900 1150 50  0001 C CNN
+F 1 "+3V3" H 3915 1473 50  0000 C CNN
+F 2 "" H 3900 1300 50  0001 C CNN
+F 3 "" H 3900 1300 50  0001 C CNN
+	1    3900 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+3V3 #PWR0106
+U 1 1 5D6F6B97
+P 1750 1500
+F 0 "#PWR0106" H 1750 1350 50  0001 C CNN
+F 1 "+3V3" H 1765 1673 50  0000 C CNN
+F 2 "" H 1750 1500 50  0001 C CNN
+F 3 "" H 1750 1500 50  0001 C CNN
+	1    1750 1500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1750 1500 1750 1650
+$Comp
+L power:+3V3 #PWR0107
+U 1 1 5D6F753F
+P 2550 2900
+F 0 "#PWR0107" H 2550 2750 50  0001 C CNN
+F 1 "+3V3" H 2565 3073 50  0000 C CNN
+F 2 "" H 2550 2900 50  0001 C CNN
+F 3 "" H 2550 2900 50  0001 C CNN
+	1    2550 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:+3V3 #PWR0109
+U 1 1 5D6FB5F9
+P 3900 3050
+F 0 "#PWR0109" H 3900 2900 50  0001 C CNN
+F 1 "+3V3" H 3915 3223 50  0000 C CNN
+F 2 "" H 3900 3050 50  0001 C CNN
+F 3 "" H 3900 3050 50  0001 C CNN
+	1    3900 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND #PWR0110
+U 1 1 5D6FC140
+P 3900 3300
+F 0 "#PWR0110" H 3900 3050 50  0001 C CNN
+F 1 "GND" H 3905 3127 50  0000 C CNN
+F 2 "" H 3900 3300 50  0001 C CNN
+F 3 "" H 3900 3300 50  0001 C CNN
+	1    3900 3300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3900 3050 3900 3100
+Wire Wire Line
+	3900 3100 4250 3100
+Wire Wire Line
+	3900 3300 3900 3200
+Wire Wire Line
+	3900 3200 4250 3200
+Wire Wire Line
+	3100 1650 3100 1550
+Connection ~ 3100 1650
+Wire Wire Line
+	3100 1650 3200 1650
+NoConn ~ 2750 1150
+NoConn ~ 2650 1150
+NoConn ~ 2550 1150
+NoConn ~ 2450 1150
+NoConn ~ 2350 1150
+NoConn ~ 2650 2150
+Wire Wire Line
+	2900 1750 3050 1750
+$Comp
+L RF_Module:RFM95W-868S2 U2
+U 1 1 5D664943
+P 2450 1650
+F 0 "U2" V 2350 2100 50  0000 L CNN
+F 1 "RFM95W-868S2" V 2250 2100 50  0000 L CNN
+F 2 "RFM:RFM95" H -850 3300 50  0001 C CNN
+F 3 "https://www.hoperf.com/data/upload/portal/20181127/5bfcbea20e9ef.pdf" H -850 3300 50  0001 C CNN
+	1    2450 1650
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	3050 1550 3100 1550
+Wire Wire Line
+	3050 1750 3100 1750
+Wire Wire Line
+	3100 1750 3100 1650
+Connection ~ 3050 1750
+Wire Wire Line
+	1750 1650 1950 1650
+$EndSCHEMATC
diff --git a/PCB_THT/LORA_ATTINY84_nonsmd.jpg b/PCB_THT/LORA_ATTINY84_nonsmd.jpg
new file mode 100644
index 0000000..0a7b9ad
Binary files /dev/null and b/PCB_THT/LORA_ATTINY84_nonsmd.jpg differ
diff --git a/PCB_THT/README.md b/PCB_THT/README.md
new file mode 100644
index 0000000..352b428
--- /dev/null
+++ b/PCB_THT/README.md
@@ -0,0 +1,12 @@
+# TinyLora PCB (Throughole Version)
+
+PCB for the TinyLora Sensor Node, Throughole Version 
+WARNING: Due to height might not fit into the 3D-Printed case when ATTiny is used with a Socket
+
+## Parts List
+
+*  ATTiny84A-PU (DIL-14) MCU
+*  HopeRF RFM95W Lora Module
+*  SMD CR2032 Battery Holder (see pictures in main directory for type I used)
+*  2x3 Pin 2.54mm Pitch Pinheader for PRG1 optional
+*  1x8 Pin 2.54mm Pitch Pinheader for J1 (only if not meant to be put into the case), optional
diff --git a/PCB_THT/fp-info-cache b/PCB_THT/fp-info-cache
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/PCB_THT/fp-info-cache
@@ -0,0 +1 @@
+0
diff --git a/PCB_THT/fp-lib-table b/PCB_THT/fp-lib-table
new file mode 100644
index 0000000..e81599e
--- /dev/null
+++ b/PCB_THT/fp-lib-table
@@ -0,0 +1,4 @@
+(fp_lib_table
+  (lib (name RFM)(type KiCad)(uri /data/Git/IOT/attiny84_lora_nonsmd/RFM95)(options "")(descr ""))
+  (lib (name battery_holder)(type KiCad)(uri /data/Git/IOT/attiny84_lora/battery_holder.pretty)(options "")(descr ""))
+)
diff --git a/README.md b/README.md
index 4d8eba5..cfa9851 100644
--- a/README.md
+++ b/README.md
@@ -12,13 +12,13 @@ A Minimalistic Sensor Node for use on TheThingsNetwork.
 
 ### Features
 
-* Small Size, only 47x36x15mm populated
+* Small Size, only 47x36x15mm populated (SMD Version)
 * Based on widely available Atmel ATTiny84 MCU and RFM95W LoRa-module
 * 6 free GPIO-Pins from the ATTiny + Power to connect sensors on a 2.54mm pitch header
-* Optional on-board LED for status signaling
+* Optional on-board LED for status signaling (SMD Version)
 * Powered by a single CR2032 lithium battery
 * Long battery runtime using  the ATTinys deep sleep mode
-* Integrated 6-Pin programming header
+* Integrated 6-Pin programming header (SMD Version)
 * Small component count
 
 ## Subdirectories In this Repository
@@ -50,4 +50,4 @@ A Minimalistic Sensor Node for use on TheThingsNetwork.
 |      5 | PA2      |                                |
 |      6 | PA3      |                                |
 |      7 | PA7      | Connected to LED-Pad D1 via R1 |
-|      8 | PB2      |                                |
\ No newline at end of file
+|      8 | PB2      |                                |